A voltage level shifter circuit is required whenever a signal must be transferred from one circuit operating at a lower voltage level to another circuit operating at a higher voltage level. In typical logic circuits, devices such as logic gates or components operate at lower voltage levels, while devices such as electrically programmable read-only memories (EPROM's) operate at higher voltage levels. As one example, in a first circuit operating at a lower voltage level the signal voltage varies between 0 and 5 volts, while in a second circuit operating at a higher voltage level the signal voltage varies between 0 and 18 volts. In the latter example, in order to transfer the signal from the first circuit to the second circuit, the peak voltage level of the signal must first be shifted by a voltage level shifter circuit from 5 volts to 18 volts.
FIG. 1 shows a typical prior art digital level shifter circuit including a first inverter 10 having a P-channel MOS (PMOS) transistor 11 and an N-channel MOS (NMOS) transistor 13 forming a first CMOS transistor pair. The source of the PMOS transistor 11 is connected to a first voltage supply V.sub.CC, the source of the NMOS transistor 13 being grounded while the drains of the transistors 11, 13 are connected to an output 14. The output 14 is connected to the gates of a second CMOS transistor pair comprising a PMOS transistor 16 and an NMOS transistor 17 in a second inverter 15. A signal applied to input node 12 of the first inverter 10 is inverted at the output 14. The inverted signal is then reinverted by the inverter 15. The source of the PMOS transistor 16 is connected to a second voltage supply V.sub.DD characterized by a higher voltage than the first voltage supply so that the re-inverted signal at output node 18 of the second inverter 15 has a peak voltage shifted up or increased with respect to the peak voltage of the signal at the input node 12.
During each transition of the signal at the input node 12 between 0 volts and its peak voltage (5 volts, for example), both of the transistors 16 and 17 in the second inverter 15 may be on, but after such a transition is finished one or the other of the transistors 16, 17 should be off (virtually non-conducting) in order to prevent direct current power dissipation from the voltage supply V.sub.DD to ground. The disadVantage of the level shifter circuit of FIG. 1 is that the PMOS transistor 16 has a tendency to remain on as a consequence of its threshold voltage even after the NMOS transistor 17 has turned on following a transition by the input signal. With both transistors on, a path exists permitting DC power dissipation, a significant problem.
FIG. 2 shows a level shifter circuit disclosed in U.S. Pat. No. 4,486,670 which prevents DC power dissipation of the type experienced in the level shifter circuit of FIG. 1. However, a significant disadvantage of the level shifter circuit of FIG. 2 is that it requires two different voltage supplies V.sub.CC and V.sub.DD for the two inverters 20, 25 and for the latch circuit 30.
FIG. 3 illustrates another conventional solution to the DC power consumption problem. The level shifter of FIG. 3 includes an inverter 40 and a latch circuit 45. Because not all the transistors of the complementary transistor pairs in the latch circuit 45 will be turned on after each transition of the input signal, there is no direct current path from the voltage supply V.sub.DD to ground. This feature solves the problem of DC power consumption. However, another problem exists in that two power supplies V.sub.CC and V.sub.DD characterized by different voltages are required to perform voltage level shifting.
A linear type MOS level shifter circuit 55 is shown in FIG. 4. It includes a current source NMOS transistor 61, a pair of current mirror PMOS transistors 56, 57 whose gates are connected together to the drain of the PMOS transistor 56, and two input stage NMOS transistors 60, 62. Only a single voltage supply V.sub.DD is required and it is connected to the sources of the PMOS transistors 56, 57. Gate 63 of the NMOS transistor 62 receives a reference signal which governs the difference between the voltage at input node 59 and the voltage at output node 64. A bias voltage V.sub.B is applied to the gate of the current source transistor 61. The disadvantage of the level shifter of FIG. 4 is that there is significant DC power consumption through the transistor 61.
In summary, it would seem that a voltage level shifter circuit can enjoy only one of two distinct advantages, but not both, namely that the circuit either requires only a single voltage supply or else the circuit has low DC power consumption. Thus, there is a need for a voltage level shifter circuit which provides both advantages simultaneously.